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december 2009 ? 2007 fairchild semiconductor corporation www.fairchildsemi.com fsusb46 ? rev. 1.0.4 fsusb46 ? hi-speed usb2.0 (480mbps) dpst switch with dedicated charger port detection click here for this datasheet translated into chinese! fsusb46 ? hi-speed usb2.0 (480mbps) dpst switch with dedicated charger port detection features ? low on capacitance: 7.0pf typical ? low on resistance: 3.9 ? typical ? low power consumption: 1 a maximum - 15 a maximum i cct over an expanded voltage range (v in =1.8v, v cc =4.3v) ? wide -3db bandwidth: > 720mhz ? packaged in pb-free, 8-lead micropak? (1.6mm wide), us8 (3.1mm wide), and umlp (1.4x1.4mm) ? 8kv esd rating, >16kv power/gnd esd rating ? power-off protection on all ports when v cc =0v - d+/d- pins tolerate up to 5.25v applications ? cell phone, pda, digital camera, and notebook ? lcd monitor, tv, and set-top box important note : for additional performance info rmation, please contact analogswitch@fairchildsemi.com . description the fsusb46 is a bi-directional, low-power, hi-speed, usb2.0 switch. configured as a double-pole, single- throw switch (dpst) switch, it is optimized for switching a hi-speed (480mbps) source. the fsusb46 is compatible with the requirements of usb2.0 and features an extremely low on capacitance (c on ) of 3.9pf. the wide bandwidth of this device (720mhz) exceeds the bandwidth needed to pass the third harmonic, resulting in signals with minimum edge and phase distortion. superior channel-to-channel crosstalk also minimizes interference. the fsusb46 contains special circuitry on the switch i/o pins for applications where the v cc supply is powered-off (v cc =0), which allows the device to withstand an over-voltage condition. this device is designed to minimize current consumption even when the control voltage applied to the /oe pin is lower than the supply voltage (v cc ). this feature is especially valuable to ultra-portable applications, such as cell phones, allowing for direct interface with the general- purpose i/os of the baseband processor. an additional feature is the detection of the 1-1 (high/high) state on d+/d- to signal an interrupt (int) to the processor when entering a dedicated charging port mode of operation. ordering information part number operating temperature range package eco status fsusb46l8x -40 to +85c 8-lead micropak? 1.6mm wide rohs fsusb46k8x -40 to +85c 8-lead us8, jedec mo187, variation ca 3.1mm green FSUSB46UMX -40 to +85c 8-lead ultrathin molded leadless package (umlp), 1.2 x 1.4mm green for fairchild?s definition of eco status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html . micropak? is a trademark of fairchild semiconductor corporation. figure 1. analog symbol
? 2007 fairchild semiconductor corporation www.fairchildsemi.com fsusb46 ? rev. 1.0.4 2 fsusb46 ? hi-speed usb2.0 (480mbps) dpst switch with dedicated charger port detection pin configurations 8 7 6 5 1 3 v cc 2 4 gnd /oe hsd+ d+ int hsd ? d? figure 2. micropak? (top through view) figure 3. us8 (top through view) figure 4. umlp (top through view) pin definitions pin name description int interrupt signaling output pin /oe switch enable d+, d- usb data bus connector hsd+, hsd- usb source inputs gnd ground v cc supply voltage truth table data path charger detect path /oe switch connection d+ d- int output high d+, d- = open 1-1 low low d+, d- = hsd+, hsd- 0x, x0 high
? 2007 fairchild semiconductor corporation www.fairchildsemi.com fsusb46 ? rev. 1.0.4 3 fsusb46 ? hi-speed usb2.0 (480mbps) dpst switch with dedicated charger port detection absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter min. max. unit v cc supply voltage -0.5 +5.5 v v cntrl dc input voltage (s) (1) -0.5 v cc v v sw dc switch i/o voltage (1) -0.50 5.25 v i ik dc input diode current -50 ma i out dc output current 50 ma t stg storage temperature -65 +150 c esd human body model, jedec: jesd22-a114 all pins 7 kv i/o to gnd 8 power to gnd 16 charged device model, jedec: jesd22-c101 2 note : 1. the input and output negative ratings may be exceeded if t he input and output diode current ratings are observed. recommended operating conditions the recommended operating conditions table defines the conditions for actual device operation. recommended operating conditions are specified to ens ure optimal performance to the datasheet specifications. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter min. max. unit v cc supply voltage 3.0 4.3 v v cntrl control input voltage (/oe) (2) 0 v cc v v sw switch i/o voltage -0.5 v cc v t a operating temperature -40 +85 c note : 2. the control input must be held high or low; it must not float.
? 2007 fairchild semiconductor corporation www.fairchildsemi.com fsusb46 ? rev. 1.0.4 4 fsusb46 ? hi-speed usb2.0 (480mbps) dpst switch with dedicated charger port detection dc electrical characteristics all typical value are at 25c, v cc =3.3v unless otherwise specified. symbol parameter conditions v cc (v) t a =- 40oc to +85oc units min. typ. max. v ik clamp diode voltage i in =-18ma 3.0 -1.2 v v ih input voltage high 3.0 to 3.6 1.3 v 4.3 1.7 v v il input voltage low 3.0 to 3.6 0.5 v 4.3 0.7 v v oh output voltage high i oh =-2ma 3.0 to 3.6 2.4 v 4.3 2.4 v ol output voltage low i ol =2ma 3.0 to 3.6 0.25 v 4.3 0.25 i in control input leakage v sw =0 to v cc 4.3 -1 1 a i oz off state leakage hsd+ or hsd-=0v, 3.6v or floating 4.3 -2 2 a i off power-off leakage current (all i/o ports) v sw =0v to 4.3v, v cc =0v figure 6 0 -2 2 a r on hs switch on resistance (3) v sw =0.4v, i on =-8ma figure 5 3.0 3.9 6.5 ? r on hs delta r on (4) v sw =0.4v, i on =-8ma 3.0 0.65 i cc quiescent supply current v cntrl =0 or v cc , i out =0 4.3 1 a i cct increase in i cc current per control voltage and v cc v cntrl =2.6v v cc =4.3v 4.3 10 a v cntrl =1.8v v cc =4.3v 4.3 20 a notes : 3. measured by the voltage drop between hsdn and dn pi ns at the indicated current through the switch. on resistance is determined by the lower of the voltage on the two (hsdn or dn ports). 4. guaranteed by characterization.
? 2007 fairchild semiconductor corporation www.fairchildsemi.com fsusb46 ? rev. 1.0.4 5 fsusb46 ? hi-speed usb2.0 (480mbps) dpst switch with dedicated charger port detection ac electrical characteristics all typical value are for v cc =3.3v at 25c unless otherwise specified. symbol parameter conditions v cc (v) t a =- 40oc to +85oc units min. typ. max. t on turn-on time /oe to output r l =50 ? , c l =5pf v sw =0.8v figure 7, figure 8 3.0 to 3.6 13 30 ns t off turn-off time /oe to output r l =50 ? , c l =5pf v sw= 0.8v figure 7, figure 8 3.0 to 3.6 12 25 ns t pd propagation delay (5) c l =5 pf, r l =50 ? figure 7, figure 9 3.3 0.25 ns t bbm break-before-make r l =50 ? , c l =5pf v sw1 =v sw2 =0.8v figure 13 3.0 to 3.6 2.0 6.5 ns t plh/hl int propagation delay (5) r l =500 ? , c l =5pf 3.0 to 3.6 10 ns o irr off isolation r l =50 ? , f=240mhz figure 15 3.0 to 3.6 -30 db xtalk non-adjacent channel crosstalk r l =50 ? , f=240mhz figure 16 3.0 to 3.6 -45 db bw -3db bandwidth r l =50 ? , c l =0pf figure 14 3.0 to 3.6 720 mhz r l =50 ? , c l =5pf figure 14 550 mhz note : 5. guaranteed by characterization. usb hi-speed-related ac electrical characteristics symbol parameter conditions v cc (v) t a =- 40oc to +85oc units min. typ. max. t sk(p) skew of opposite transitions of the same output (6) c l =5pf, r l =50 ? figure 10 3.0 to 3.6 20 ps t j total jitter (6) r l =50 ? , c l =5pf, t r =t f =500ps (10-90%) at 480mbps (prbs=2 15 ? 1) 3.0 to 3.6 200 ps note : 6. guaranteed by characterization. capacitance symbol parameter conditions t a =- 40oc to +85oc units min. typ. max. c in control pin input capacitance v cc =0v 1.5 pf c out int pin output capacitance v cc =0v 2.5 pf c on d+, d- on capacitance v cc =3.3v, f=1mhz figure 12 7.0 7.9 pf c off d+, d- off capacitance v cc =3.3v figure 11 2.0 pf
? 2007 fairchild semiconductor corporation www.fairchildsemi.com fsusb46 ? rev. 1.0.4 6 fsusb46 ? hi-speed usb2.0 (480mbps) dpst switch with dedicated charger port detection test diagrams figure 5. on resistance figure 6. off/on leakage r l ,r s ,a nd c l a re f un ctions of the a pp lication environment (s ee ac tables for sp ec ific va lue s) c l incl ud es test fixture a nd str ay capacitanc e. r l c l hsd n dn gnd gnd r s v sel v sw gnd v out v out figure 7. ac test circuit load figur e 8. turn-on / turn-off waveforms input output v oh v ol 50% 50% 50% 50% 400mv t phl t plh 0v t rise = 500ps -400mv 90% 90% 10% 10% t fall =500ps 0v output t phl +400mv t plh figure 9. propagation delay (t r t f ? 500ps) figure 10. intra-pair skew test t sk(p) figure 11. channel off capacitance figure 12. channel on capacitance /oe hsd n dn v oe = 0 o v cc i on v on r on = v on /i on gnd v sw gnd sw t rise =2.5ns gnd v cc 90 %90% 10% 10 % t fall =2.5n s v cc /2 v cc /2 input ?v /oe output- v out 90% v oh v ol t on t off 90% v ?v v ? 0 o r v cc hsd n capacitance mete r /oe hsd n v /oe = 0 o r v cc hsd n capa c itance mete r /oe hsd n
? 2007 fairchild semiconductor corporation www.fairchildsemi.com fsusb46 ? rev. 1.0.4 7 fsusb46 ? hi-speed usb2.0 (480mbps) dpst switch with dedicated charger port detection test diagrams (continued) 0. 9 * / 2 0v - 0.9 * = 2.5ns 90 % 10% hsd n dn - - gnd gnd v /oe v sw1 gnd r l c l r s v /oe input v out v cc v cc v out v ou t t rise t bbm r l , r s , and c l are functions of the application environment (see ac table for specific values). cl includes text ficture and stray capacitance. figure 13. break-before-make interval timing network analyzer v in v /oe gnd gnd gnd gnd gnd v out r s v s r t r s , and r t are functions of the application environment (see ac table for specific values). figure 14. bandwidth v s network analyzer off isolation = 20 log ( v out /v in ) r s , and r t are functions of the application environment (see ac table for specific values). gnd gnd gnd gnd v /oe v out v in r s r t figure 15. channel off isolation network analyzer nc r s , and r t are functions of the application environment (see ac table for specific values). crosstalk = 20 log ( v out /v in ) gnd v /oe r t gnd v /oe v out r t r t v s r s gnd gnd gnd gnd v in figure 16. non-adjacent channel-to-channel crosstalk
? 2007 fairchild semiconductor corporation www.fairchildsemi.com fsusb46 ? rev. 1.0.4 8 fsusb46 ? hi-speed usb2.0 (480mbps) dpst switch with dedicated charger port detection physical dimensions (0 .0 9 ) (0 .1 ) (0 .2 ) 1 .6 2 x 0 .0 5 0 .0 0 1 .6 2 x c 0 .0 5 c 4 3 . d r a w in g c o n f o r m s t o a s m e y .1 4 m -1 9 9 4 2 . d im e n s io n s a r e in m il l im e t e r s 1 . p a c k a g e c o n f o r m s t o j e d e c m o -2 5 5 v a r ia t io n u a a d b o t t o m v ie w 4 . p in 1 f l a g , e n d o f p a c k a g e o f f s e t m a c 0 8 a r e v 4 1 2 3 5 6 7 8 n o te s : 8 x 0 .2 5 0 .3 5 3 x 8 x 1 .0 4 0 .5 8 x 0 .2 5 0 .1 5 0 .1 0 c a b 0 .0 5 c 0 .1 0 c t o p v ie w in d e x a r e a b r e c o m m e n d e d l a n d p a tte rn a 0 .1 0 c 0 .5 5 m a x 0 .0 5 c d e t a il a 0 .3 5 0 .2 5 (0 .1 5 ) (0 .2 0 ) 0 .3 5 0 .2 5 d e t a il a p in # 1 t e r m in a l s c a l e : 2 x 5 . d r a w in g f il e n a m e : m k t -m a c 0 8 a r e v 4 figure 17. 8-lead micropak? package drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and condition s, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ .
? 2007 fairchild semiconductor corporation www.fairchildsemi.com fsusb46 ? rev. 1.0.4 9 fsusb46 ? hi-speed usb2.0 (480mbps) dpst switch with dedicated charger port detection tape and reel specifications package designator tape section cavity number cavity status cover tape status l6x, l8x, l10x leader (start end) 125 (typical) empty sealed carrier 5000 filled sealed trailer (hub end) 75 (typical) empty sealed standard tape and reel specifications standard tape and reel specifications for micropak ar e available at fairchild semiconductor?s website: http://www.fairchildsemi.com/products/logic/pdf/micropak_tr.pdf fsusb46l8x_f130 tape and reel specifications 10 30056 2.30 0.1mm 1.78 0.1mm 0.68 0.1mm 8 30038 1.78 0.1mm 1.78 0.1mm 0.68 0.1mm 6 30033 1.60 0.1mm 1.15 0.1mm 0.70 0.1mm
? 2007 fairchild semiconductor corporation www.fairchildsemi.com fsusb46 ? rev. 1.0.4 10 fsusb46 ? hi-speed usb2.0 (480mbps) dpst switch with dedicated charger port detection physical dimensions 0.30 typ seating plane 0.10-0.18 0.13 ab c c. dimensions are exclusive of burrs, mold flash, d. dimensions and tolerances per ansi y14.5m, 1982. and tie bar extrusions. mab08arevc 0.50typ b. dimensions are in millimeters. a. conforms to jedec registration mo-187 -c- 0.17-0.27 0.10 0.00 detail a 0-8 0.4 typ -b- 0.700.10 all lead tips 0.2 c b a 3.1.1 0.15 pin #1 ident. 0.90 max all lead tips 0.1 c 1.55 8 1 4 2.30.1 5 -a- 0.70 2.70 3.40 1.00 0.5 typ detail a 1.80 gage plane 0.12 figure 18. 8-lead us8, jedec mo-187 for current tape and reel specifications, visit fairchild semiconductor?s online packaging area: http://www.fairchildsemi.com/ms/ms/ms-522.pdf package drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and condition s, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/ packaging / .
? 2007 fairchild semiconductor corporation www.fairchildsemi.com fsusb46 ? rev. 1.0.4 11 fsusb46 ? hi-speed usb2.0 (480mbps) dpst switch with dedicated charger port detection physical dimensions 1.20 1.4 5 2 0.35 0.25 7x (0.2) 0.15 0.25 seating plane 0.40 0.10 cab 0.05 c 2x 2x 0.025 0.00 c 0.10 a c 0.10 a. does not conforms to jedec standard. c 0.05 b c 0.05 pin#1 ident 0.55 max c bottom view top view 8 1 6 4 notes: b. dimensions are in millimeters. c. dimensions and tolerances conforms to asme y14.5m, 1994. d. drawing file name : umlp08arev1 8x detail a detail: a scale : 2x 0.30 0.20 0.10 45 0.10 0.400 0.250 8x 0.350 7x 0.450 1.250 0.625 1.450 0.725 figure 19. 8-lead, ultrathin molded leadless package (umlp), 1.2 x 1.4mm package drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and condition s, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ .
? 2007 fairchild semiconductor corporation www.fairchildsemi.com fsusb46 ? rev. 1.0.4 12 fsusb46 ? hi-speed usb2.0 (480mbps) dpst switch with dedicated charger port detection

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